Double data rate II(DDR2)SDRAM can increase the data transmission bandwidth by leaps and bounds by increasing the I/O clock to twice that of DDR,which provides stable and reliable data buffering support for communication equipment,industrial control and embedded systems.Based on the balanced design of cost-effectiveness and reliability,DDR2 SDRAM can be widely used in network switches,base station control boards,high-definition video processing equipment and industrial automation controllers.
EM68256WQCA is a CMOS DDR2 SDRAM that meets the industry standard,with a storage capacity of 256 megabits and a 16-bit data I/O wide port design.The internal logical architecture of SDRAM is a four-bank structure,and each bank contains 4Mb address space,which significantly improves the random access efficiency through parallel operation mode.Its design strictly follows DDR2 standard protocol,integrates issuing CAS(column address gating)and additional delay function,supports sequential logic that the write delay is equal to the read delay minus one,and effectively optimizes the instruction pipeline.
The dynamic random access memory EM68256WQCA DDR2 SDRAM adopts source synchronous bidirectional data strobe(DQS and DQS#),and the read-write access to DDR2 SDRAM is 4 or 8-bit burst oriented;Access the location in the programming sequence from the selected number of times to locate and continue programming.Operating four banks in an interleaved manner allows random access operations to be higher than for standard DRAMs.SDRAM Auto-precharge can enable the function to provide a precharge sequence that is started by a self-timed line at the end of a burst.The continuous gapless data rate may depend on the burst length,CAS delay and the speed class of the device.
Characteristics of SDRAM dynamic random access memory EM68256WQCA
?、賑omply with JEDEC standards.
?、赑ower supply:+1.8V 0.1V.
?、踂orking temperature:0~85 C.
?、躶upport JEDEC clock jitter specification.
?、軨omplete synchronous operation.
?、轋ast clock rate:333/400/533 MHz.
?、連idirectional Single/Differential Data Gating
⑧Internal pipeline architecture
?、酨et-name ruby programmable mode and extended mode register
Keywords:
SDRAM
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